SoftCPU: A flexible and simple CPU design in FPGA for educational purpose

Abstract

Dealing with a high-performance graphics system in the embedded system domain is always a difficult job. Due to its high practicality, flexibility, efficiency, and cost per unit, the Field Programmable Gate Array (FPGA) has gained considerable attention in recent years for developing Graphics Frameworks on its processor. I provide design views and a schematic layout for the Graphics framework, which is used to implement graphics capabilities on FPGA-based 8-bit processors. I have built an 8-bit processor using the ISE (Integrated Synthesis Environment) design suite and then tested and validated it on both software and hardware using the ISim (ISE Simulator) and a Xilinx Spartan-6 LX16 FPGA. The processor framework was designed using the Hardware Description Language (Verilog). The initial purpose of this research was to create real-time primitive projections of basic wireframe models on a single chip. As a result, I develop an 8-bit RISC-based SoftCPU. Although this difficulty extends beyond the capabilities of conventional microcontrollers/CPUs, the answer has resulted in the development of a hardware graphics pipeline capable of drawing on a screen through the VGA interface in conjunction with a monitor.