Yan Li, Seungpil Lee, K. Oowada, Hao Nguyen, Q. Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, T. Kamei, M. Higashitani, T. Pham, M. Honma, Y. Watanabe, K. Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, F. Tsai, Kwang-Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, A. Chu, Cheng Chen, R. Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, J. Chan, Mitsuyuki Watanabe, Dan Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, T. Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, J. Lan, E. Yero, Feng Pan, Patrick Hong, Jang Yong Kang, F. Moogat, Y. Fong, R. Cernea, S. Huynh, Cuong Trinh, M. Mofidi, Ritu Shrivastava, K. Quader
{"title":"128Gb 3b/cell NAND flash memory in 19nm technology with 18MB/s write rate and 400Mb/s toggle mode","authors":"Yan Li, Seungpil Lee, K. Oowada, Hao Nguyen, Q. Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, T. Kamei, M. Higashitani, T. Pham, M. Honma, Y. Watanabe, K. Ino, Binh Le, Byungki Woo, Khin Htoo, Taiyuan Tseng, Long Pham, F. Tsai, Kwang-Ho Kim, Yi-Chieh Chen, Min She, Jonghak Yuh, A. Chu, Cheng Chen, R. Puri, Hung-Szu Lin, Yi-Fang Chen, William Mak, Jonathan Huynh, J. Chan, Mitsuyuki Watanabe, Dan Yang, Grishma Shah, Pavithra Souriraj, Dinesh Tadepalli, T. Suman, Ray Gao, Viski Popuri, Behdad Azarbayjani, Ravindra Madpur, J. Lan, E. Yero, Feng Pan, Patrick Hong, Jang Yong Kang, F. Moogat, Y. Fong, R. Cernea, S. Huynh, Cuong Trinh, M. Mofidi, Ritu Shrivastava, K. Quader","doi":"10.1109/ISSCC.2012.6177080","DOIUrl":null,"url":null,"abstract":"This paper addresses challenges with improvements made over previous NAND generations to achieve high performance while maintaining a low fail-bit count (FBC) and cost savings from an improved architecture and tightly packed peripheral circuits. Air gap [2,3] technology further improves write throughput by reducing neighbor interference and WL RC. A toggle mode 400Mb/s I/O interface reduces system overhead and enhances overall performance.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"44","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2012.6177080","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 44
Abstract
This paper addresses challenges with improvements made over previous NAND generations to achieve high performance while maintaining a low fail-bit count (FBC) and cost savings from an improved architecture and tightly packed peripheral circuits. Air gap [2,3] technology further improves write throughput by reducing neighbor interference and WL RC. A toggle mode 400Mb/s I/O interface reduces system overhead and enhances overall performance.