A ROBUST LOW POWER FSM CORDIC LMS FILTER DESIGN for EXPONENTIAL NOISE REMOVAL in PACEMAKER

Abstract

ABSTRACTHeart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The Least mean square (LMS) filter with Co-ordinate Rotation Digital Computer(CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies leakage power has started to occupy 30-50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, Integrated coarse grained Power and Clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch, AND and OR based clock gating with Forced transistor stacking and sleep transistor whose width and length is doubled from the rest of the Complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques is found to be 36.95% from the non-gated CORDIC LMS filter design.KEYWORDS: Clock gatingpower gatingpacemakerCORDIC algorithmLMS filterDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.