The ARTEMIS project: Mixed-Signal IC for Edge-AI-based Classification of ECG Signals

Ingo Hoyer, Alexander Utz, André Lüdecke, Karsten Seidl, Özgü Roßman, Lukas Straczek, Onur Akboyraz, Sebastian Hessel
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Abstract

Abstract Atrial fibrillation (AF) is a common heart arrhythmia and is closely associated with causing strokes. Diagnosis is usually performed with Holter monitors over longer periods of time, causing discomfort to the patient. The proposed mixed-signal integrated circuit (IC) is designed for small patch electrocardiogram (ECG) devices and combines, an analog front-end (AFE) with tailored recording channel characteristics and 12-bit successive-approximation-register analog digital converter (SAR ADC) as well as an RISC-V based microcontroller (μC) for edge artificial intelligence (AI)-based AF-detection. The digital signal processing is supported with hardware accelerators. Including 160 kB of SRAM, the system on chip (SoC) requires 25.56 mm² in silicon area in a 180 nm technology. The recording channel shows promising simulation results with an input impedance of 230 MΩ, an input referred noise of below 1.6 μVrms and a CMMR of 95 dB. The digital part enables the integration of AI-based classification on the IC. Due to the flexibility of the software-based classification approach, this IC can also be used to detect other arrhythmias.
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ARTEMIS项目:基于边缘人工智能的心电信号分类混合信号IC
心房颤动(AF)是一种常见的心律失常,与脑卒中的发生密切相关。诊断通常是通过更长时间的动态心电图来进行的,这会给病人带来不适。所提出的混合信号集成电路(IC)是为小贴片心电图(ECG)设备设计的,结合了具有定制记录通道特性的模拟前端(AFE)和12位连续逼近寄存器模拟数字转换器(SAR ADC),以及基于RISC-V的微控制器(μC),用于基于边缘人工智能(AI)的af检测。硬件加速器支持数字信号处理。包括160 kB的SRAM,系统片上(SoC)在180纳米技术中需要25.56 mm²的硅面积。该记录通道的输入阻抗为230 MΩ,输入参考噪声低于1.6 μVrms, CMMR为95 dB,仿真结果令人满意。数字部分可以将基于人工智能的分类集成到集成电路上。由于基于软件的分类方法的灵活性,该集成电路也可以用于检测其他心律失常。
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来源期刊
Current Directions in Biomedical Engineering
Current Directions in Biomedical Engineering Engineering-Biomedical Engineering
CiteScore
0.90
自引率
0.00%
发文量
239
审稿时长
14 weeks
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