Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2

IF 3.1 4区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Transactions on Reconfigurable Technology and Systems Pub Date : 2023-09-15 DOI:10.1145/3624571

Louis Noyez, Nadia El Mrabet, Olivier Potin, Pascal Veron

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Abstract

This paper describes an extensive study of the use of DSP48E2 Slices in Ultrascale FPGAs to design hardware versions of the Montgomery Multiplication algorithm for the hardware acceleration of modular multiplications. Our fully scalable systolic architectures result in parallelized, DSP48E2-optimized scheduling of operations analogous to the FIOS block variant of the Montgomery Multiplication. We explore the impacts of different pipelining strategies within DSP blocks, scheduling of operations, processing element configurations, global design structures and their trade-offs in terms of performance and resource costs. We discuss the application of our methodology to multiple types of DSP primitives. We provide ready to use fast, efficient and fully parametrizable designs which can adapt to a wide range of requirements and applications. Implementations are scalable to any operand width. Our most efficient designs can perform 128, 256, 512, 1024, 2048 and 4096 bits Montgomery modular multiplications in 0.0992 μ s, 0.2032 μ s, 0.3952 μ s, 0.7792 μ s, 1.550 μ s and 3.099 μ s using 4, 6, 11, 21, 41 and 82 DSP blocks respectively.

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针对DSP48E2优化的Montgomery倍增可伸缩收缩设计

本文描述了在Ultrascale fpga中使用DSP48E2切片的广泛研究，以设计用于模块化乘法硬件加速的Montgomery乘法算法的硬件版本。我们完全可扩展的收缩架构导致并行化，dsp48e2优化的操作调度，类似于蒙哥马利乘法的FIOS块变体。我们探讨了DSP块内不同的流水线策略、操作调度、处理元素配置、全局设计结构及其在性能和资源成本方面的权衡的影响。我们讨论了我们的方法在多种类型的DSP原语中的应用。我们提供随时可用的快速，高效和完全可参数化的设计，可以适应广泛的要求和应用。实现可扩展到任何操作数宽度。我们最有效的设计可以在0.0992 μ s、0.2032 μ s、0.3952 μ s、0.7792 μ s、1.550 μ s和3.099 μ s内分别使用4、6、11、21、41和82个DSP块执行128、256、512、1024、2048和4096位蒙哥马利模乘法。

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来源期刊

ACM Transactions on Reconfigurable Technology and Systems COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.90

自引率

8.70%

发文量

审稿时长

>12 weeks

期刊介绍： TRETS is the top journal focusing on research in, on, and with reconfigurable systems and on their underlying technology. The scope, rationale, and coverage by other journals are often limited to particular aspects of reconfigurable technology or reconfigurable systems. TRETS is a journal that covers reconfigurability in its own right. Topics that would be appropriate for TRETS would include all levels of reconfigurable system abstractions and all aspects of reconfigurable technology including platforms, programming environments and application successes that support these systems for computing or other applications. -The board and systems architectures of a reconfigurable platform. -Programming environments of reconfigurable systems, especially those designed for use with reconfigurable systems that will lead to increased programmer productivity. -Languages and compilers for reconfigurable systems. -Logic synthesis and related tools, as they relate to reconfigurable systems. -Applications on which success can be demonstrated. The underlying technology from which reconfigurable systems are developed. (Currently this technology is that of FPGAs, but research on the nature and use of follow-on technologies is appropriate for TRETS.) In considering whether a paper is suitable for TRETS, the foremost question should be whether reconfigurability has been essential to success. Topics such as architecture, programming languages, compilers, and environments, logic synthesis, and high performance applications are all suitable if the context is appropriate. For example, an architecture for an embedded application that happens to use FPGAs is not necessarily suitable for TRETS, but an architecture using FPGAs for which the reconfigurability of the FPGAs is an inherent part of the specifications (perhaps due to a need for re-use on multiple applications) would be appropriate for TRETS.