An area efficient vedic multiplier for FFT Processor implementation using 4-2 compressor adder

Abstract

ABSTRACTThis article proposes a compact compressor adder of Vedic multiplication for an area-efficient FFT architecture. A standard multi-radix-24,22,23 FFT with a single-path delay feedback structure is considered. Vedic multipliers employ the Urdhva Tiryakbhyam method, which reduces redundant steps and generates parallel partial products. The proposed 4-2 compressor adders have been introduced inside the vedic multiplier to minimise carry delay and speed up the multiplication process. The vedic multiplier designed on the compressor adder saves power and gate count. The devised FFT algorithm is implemented using 45 nm CMOS technology. Simulation results show a gate reduction of 21.5% and power consumption of 18.5%. The throughput had increased to 1.86 GS/s at 186 MHz compared to existing FFT architectures.KEYWORDS: Compressor adderFast fourier transformVedic multiplierUrdhva TiryakbhyamWireless personal area networkDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. Disclosure statementNo potential conflict of interest was reported by the author.Additional informationFundingThis work is not funded by any organization or institution.