Tunable floating and grounded memristor emulator Model

IF 1.1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC International Journal of Electronics Pub Date : 2023-10-14 DOI:10.1080/00207217.2023.2267218
Sagar Surendra Prasad, Somenath Dutta, Chandan Kumar Chobey, Sanjay Kumar Dubey, Bindu Priyadarshini, Rajeev Kumar Ranjan
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Abstract

ABSTRACTA Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18μm process parameter and occupies an area of 51 × 42.5 μm2 chip-area, excluding capacitor. The circuit’s reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variations analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.KEYWORDS: Memristor emulator (MRE), Current mode (CM)Differential difference Current conveyor transconductance amplifier (DDCCTA)Pinched hysteresis loop (PHL)DisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
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可调浮接地忆阻器仿真器模型
摘要提出了一种基于差分电流输送机跨导放大器(DDCCTA)的电阻可调忆阻器仿真器。该仿真器可以在接地和浮动环境下使用。提出的设计仅包含一个有源模块和少量无源组件。此外,通过简单地改变输入端口,电路可以在增量和递减模式下工作。电路显示了一个理想的记忆电阻器的所有特性,最高可达6兆赫。该模型采用TSMC 0.18μm工艺参数进行仿真,不含电容,其芯片面积为51 × 42.5 μm2。通过对电路的非理想、非易失性、蒙特卡罗、工艺转角变化分析等研究,验证了电路的可靠性。通过串/并联组合测试了电路的适用性。为了验证实验演示,采用AD844AN和CA3080制作了样机,与理论和仿真结果吻合较好。关键词:记忆阻器仿真器(MRE),电流模式(CM)差动差电流传送带跨导放大器(DDCCTA)缩紧磁滞回线(PHL)免责声明作为对作者和研究人员的服务,我们提供此版本的接受稿件(AM)。在最终出版版本记录(VoR)之前,将对该手稿进行编辑、排版和审查。在制作和印前,可能会发现可能影响内容的错误,所有适用于期刊的法律免责声明也与这些版本有关。
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来源期刊
International Journal of Electronics
International Journal of Electronics 工程技术-工程:电子与电气
CiteScore
3.30
自引率
15.40%
发文量
110
审稿时长
8 months
期刊介绍: The International Journal of Electronics (IJE) supports technical applications and developing research at the cutting edge of electronics. Encompassing a broad range of electronic topics, we are a leading electronics journal dedicated to quickly sharing new concepts and developments the field of electronics.
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