{"title":"Design of high efficient low power static logic circuit using SG fin FET","authors":"Venkatesan RameyaSridharan, Manjunathan Alagarsamy, Balamurugan Rajangam, Lalitha Sekar","doi":"10.1080/00207217.2023.2261081","DOIUrl":null,"url":null,"abstract":"ABSTRACTThe increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor ;(CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, Gate Oxide Tunneling Leakage Current, Sub threshold Leakage Current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS Technology(SLC-SG-FinFET- INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET- INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using Noise Margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS Technology (SLC-SCLSB-22 nm CMOS),and static logic circuit using computational digital low dropout in 22 nm CMOS Technology(SLC-CDLDO-22 nm CMOS) methods respectively.KEYWORDS: Complementary metal-oxide semiconductor (CMOS)leakage power dissipation22nm CMOS technologystatic logic gatesInput dependent (INDEP) FinFETDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"26 1","pages":"0"},"PeriodicalIF":1.1000,"publicationDate":"2023-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1080/00207217.2023.2261081","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
ABSTRACTThe increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor ;(CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, Gate Oxide Tunneling Leakage Current, Sub threshold Leakage Current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS Technology(SLC-SG-FinFET- INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET- INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using Noise Margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS Technology (SLC-SCLSB-22 nm CMOS),and static logic circuit using computational digital low dropout in 22 nm CMOS Technology(SLC-CDLDO-22 nm CMOS) methods respectively.KEYWORDS: Complementary metal-oxide semiconductor (CMOS)leakage power dissipation22nm CMOS technologystatic logic gatesInput dependent (INDEP) FinFETDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
期刊介绍:
The International Journal of Electronics (IJE) supports technical applications and developing research at the cutting edge of electronics. Encompassing a broad range of electronic topics, we are a leading electronics journal dedicated to quickly sharing new concepts and developments the field of electronics.