All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits

IF 2.1 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE ACM Journal on Emerging Technologies in Computing Systems Pub Date : 2022-10-13 DOI:https://dl.acm.org/doi/10.1145/3517811
Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard
{"title":"All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits","authors":"Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard","doi":"https://dl.acm.org/doi/10.1145/3517811","DOIUrl":null,"url":null,"abstract":"<p>Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With ± 20% supply voltage and 5°C to 105°C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.</p>","PeriodicalId":50924,"journal":{"name":"ACM Journal on Emerging Technologies in Computing Systems","volume":"1 1","pages":""},"PeriodicalIF":2.1000,"publicationDate":"2022-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Journal on Emerging Technologies in Computing Systems","FirstCategoryId":"94","ListUrlMain":"https://doi.org/https://dl.acm.org/doi/10.1145/3517811","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
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Abstract

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With ± 20% supply voltage and 5°C to 105°C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.

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全自旋PUF:基于自旋传递转矩磁池的全自旋电路的面积高效可靠PUF设计
近年来,自旋转移转矩磁电池(STT-mCell)作为一种很有前途的自旋电子器件应用于内存计算(CIM)系统。然而,如何保证基于stt - mccell的全自旋电路的硬件安全性是一个挑战。在这项工作中,我们提出了一种新的基于STT-mCell的全自旋电路(all-spin PUF)的物理不可克隆功能(PUF)设计,利用了STT-mCell写入延迟的独特制造工艺变化(PV)。采用一种方法在全自旋芯片中选择合适的逻辑门来生成唯一的识别密钥。线性反馈移位寄存器(LFSR)启动All-Spin PUF,并在每个时钟周期同时生成64位签名。使用自动回写技术来稳定签名的生成。此外,还采用屏蔽方案进行签名改进。改进后签名的唯一性为49.61%。在±20%的电源电压和5°C到105°C的温度变化下,全自旋PUF显示出很强的弹性。与最先进的puf相比,我们的方法可以有效地减少硬件开销。最后,验证了全自旋PUF对新出现的建模攻击的鲁棒性。
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来源期刊
ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems 工程技术-工程:电子与电气
CiteScore
4.80
自引率
4.50%
发文量
86
审稿时长
3 months
期刊介绍: The Journal of Emerging Technologies in Computing Systems invites submissions of original technical papers describing research and development in emerging technologies in computing systems. Major economic and technical challenges are expected to impede the continued scaling of semiconductor devices. This has resulted in the search for alternate mechanical, biological/biochemical, nanoscale electronic, asynchronous and quantum computing and sensor technologies. As the underlying nanotechnologies continue to evolve in the labs of chemists, physicists, and biologists, it has become imperative for computer scientists and engineers to translate the potential of the basic building blocks (analogous to the transistor) emerging from these labs into information systems. Their design will face multiple challenges ranging from the inherent (un)reliability due to the self-assembly nature of the fabrication processes for nanotechnologies, from the complexity due to the sheer volume of nanodevices that will have to be integrated for complex functionality, and from the need to integrate these new nanotechnologies with silicon devices in the same system. The journal provides comprehensive coverage of innovative work in the specification, design analysis, simulation, verification, testing, and evaluation of computing systems constructed out of emerging technologies and advanced semiconductors
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