Parametrized low-complexity hardware architecture of an H.264-based video encoder for FPGAs

Abstract

This paper presents a scalable, efficient, and real-time intra H.264 video encoder architecture designed for FPGAs. The system achieves up to 2.3 Gbit/s throughput using parallel and pipelined architecture described in VHDL. The architecture prioritizes hardware efficiency, with all modules optimized for minimal resource usage. It proposes a parametrized encoding system and a flexible design with varying size and power requirements. As a baseline, the encoder utilizes 18K logic gates with no compression while the experimental compression ratios up to 2.7 require around 51.5K logic gates. The encoder operates efficiently at frequencies between 115 and 183 MHz. This study is important as it offers a high-speed, hardware-optimized video encoding on FPGA devices. It satisfies the demands of multi-channel encoding applications. Current encoders consume significant hardware resources, constraining the possibility of deploying multiple encoders on a single FPGA device for simultaneous encoding of multiple video channels.