Hybrid Bonding for Ultra-High-Density Interconnect

Abstract

Hybrid bonding is the technology for interchip ultra-high density interconnect at pitch smaller than 10µm. The feasibility at wafer-to-wafer level bonding with bond pad pitch of sub 0.5µm has been demonstrated with scaling limitations under exploration beyond sub-0.4µm. The heterogeneous integration of chiplets often requires die-to-wafer hybrid bonding for diverse chip stacking architectures. This overview emphasis on some main issues associated with hybrid bonding extending to die-to-wafer level. The hybrid bond pad structure design is a critical factor affecting sensitivity to overlay accuracy, copper recess or protrusion requirements, and performances. Cases of hybrid bonding schemes and pad structure designs are summarized and analyzed. Performance assessment and characterization methods are briefly over-viewed. The scalability of pad pitch is addressed by analyzing the recent literature reports. Challenges of managing sigulated dies for die-to-wafer bonding with direct placement or collective die-to-wafer bonding schemes under exploration are addressed. Nonetheless, industry collaboration for manufacturing equipment development and industry standards on handling chiplets from different technology nodes and different factories are highlighted.