Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-12-11 DOI:10.1109/LCA.2023.3341389

Courtney Golden;Dan Ilan;Caroline Huang;Niansong Zhang;Zhiru Zhang;Christopher Batten

引用次数: 0

Abstract

Recent work has explored compute-in-SRAM as a promising approach to overcome the traditional processor-memory performance gap. The recently released Associative Processing Unit (APU) from GSI Technology is, to our knowledge, the first commercial compute-in-SRAM accelerator. Prior work on this platform has focused on domain-specific acceleration using direct microcode programming and/or specialized libraries. In this letter, we demonstrate the potential for supporting a more general-purpose vector abstraction on the APU. We implement a virtual vector instruction set based on the recently proposed RISC-V Vector (RVV) extensions, analyze tradeoffs in instruction implementations, and perform detailed instruction microbenchmarking to identify performance benefits and overheads. This work is a first step towards general-purpose computing on domain-specific compute-in-SRAM accelerators.

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在商用内存计算加速器上支持虚拟矢量指令集

最近的工作探索了一种有希望克服传统处理器与内存性能差距的 "SRAM 内计算 "方法。据我们所知，GSI Technology 公司最近发布的关联处理单元（APU）是第一款商用 SRAM 内计算加速器。此前有关该平台的工作主要集中在使用直接微代码编程和/或专用库进行特定领域加速。在这封信中，我们展示了在 APU 上支持更通用矢量抽象的潜力。我们基于最近提出的 RISC-V 向量 (RVV) 扩展实现了虚拟向量指令集，分析了指令实现中的权衡，并进行了详细的指令微基准测试，以确定性能优势和开销。这项工作是在特定领域的 SRAM 计算加速器上实现通用计算的第一步。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.