JANM-IK: Jacobian Argumented Nelder-Mead Algorithm for Inverse Kinematics and its Hardware Acceleration

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-02-26 DOI:10.1109/LCA.2024.3369940

Yuxin Yang;Xiaoming Chen;Yinhe Han

引用次数: 0

Abstract

Inverse kinematics is one of the core calculations in robotic applications and has strong performance requirements. Previous hardware acceleration work paid little attention to joint constraints, which can lead to computational failures. We propose a new inverse kinematics algorithm JANM-IK. It uses a hardware-friendly design, optimizes the Jacobian-based method and Nelder-Mead method, realizes the processing of joint constraints, and has a high convergence speed. We further designed its acceleration architecture to achieve high-performance computing through sufficient parallelism and hardware optimization. Finally, after experimental verification, JANM-IK can achieve a very high success rate and obtain certain performance improvements.

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JANM-IK：用于逆运动学的 Jacobian Argumented Nelder-Mead 算法及其硬件加速算法

逆运动学是机器人应用中的核心计算之一，对性能有很高的要求。以往的硬件加速工作很少关注关节约束，这可能导致计算失败。我们提出了一种新的逆运动学算法 JANM-IK。它采用硬件友好型设计，优化了基于雅各布的方法和 Nelder-Mead 方法，实现了对关节约束的处理，并具有较高的收敛速度。我们进一步设计了其加速架构，通过充分的并行性和硬件优化实现高性能计算。最后，经过实验验证，JANM-IK 可以达到很高的成功率，并获得一定的性能提升。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.