Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-03-19 DOI:10.1109/LCA.2024.3379002

Mrinmay Sasmal;Tresa Joseph;Bindiya T. S.

引用次数: 0

Abstract

This letter introduces an innovative approximate multiplier (AM) architecture that leverages stochastically generated bit streams through the Linear Feedback Shift Register (LFSR). The AM is applied to matrix-vector multiplication (MVM) in Neural Networks (NNs). The hardware implementations in 90 nm CMOS technology demonstrate superior power and area efficiency compared to state-of-the-art designs. Additionally, the study explores applying stochastic computing to LSTM NNs, showcasing improved energy efficiency and speed.

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利用基于 LFSR 的随机序列发生器为边缘人工智能设计近似乘法器

这封信介绍了一种创新的近似乘法器（AM）架构，它通过线性反馈移位寄存器（LFSR）利用随机生成的比特流。AM 适用于神经网络 (NN) 中的矩阵向量乘法 (MVM)。与最先进的设计相比，采用 90 nm CMOS 技术的硬件实现具有更高的功耗和面积效率。此外，该研究还探索了将随机计算应用于 LSTM 神经网络，从而提高了能效和速度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.