{"title":"Enhance Speed Low Area FPGA Design Using S-Box GF and Pipeline Approach on Logic for AES","authors":"K. J. Lakshmi, G. Sreenivasulu","doi":"10.18280/mmep.110322","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":37338,"journal":{"name":"Mathematical Modelling of Engineering Problems","volume":"27 3","pages":""},"PeriodicalIF":0.0000,"publicationDate":"2024-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Mathematical Modelling of Engineering Problems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.18280/mmep.110322","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Engineering","Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
