An Investigation into the Impact of Using Automated Synthesisable Internal Power-Gating on Improved Power Efficiency for ASICs

Abstract

Automated synthesizable internal power-gating (ASIPG) offers a promising technology for enhancing the power efficiency of application precise included Circuits (ASICs). This research evaluates the possible impact of using ASIPG for the electricity efficiency of an ASIC. Multiple methods of ASIC strength consumption are tested, which include fixed voltage and frequency, dynamic frequency scaling, and strength-gating. Chip-degree information from two ASICs processing the CNN and GEMM kernels are provided to demonstrate the efficiency of ASIPG compared to traditional power-gating. The evaluation process compares the strength performance and price performance of designs that rent and do not hire ASIPG. Results suggest that designs based on ASIPG display stepped forward power performance by means of over 26% for the CNN kernel as compared to a traditional electricity-gating design and 19% for the GEMM kernel. These outcomes guide the potential of ASIPG to enhance power efficiency for ASIC designs.