Artificial Neural Network-Based Compact Model for Circuit Simulation of a 4- Transistor Active Pixel Sensor Including Conversion Gain Prediction

Abstract

This paper presents an accurate compact model to simulate a 4-transistor active pixel sensor (APS) circuit to investigate the impacts of transistor output resistances and sensing node capacitances. The compact model includes an artificial neural network-based model for the asymmetric APS transistors and an accurate capacitance model at sensing node using 3D-parasitic extraction and compositional analysis. All models are implemented in Verilog-A, and the transient characteristics for reset, integration, and readout operations of CIS are successfully reproduced in the circuit simulation. The simulation results show how the sensing node fluctuation, conversion gain, output swing, and settling time are correlated to the light intensities, parasitic capacitances of layout, and output resistances of APS transistors. This SPICE-compatible compact model provides new insights into APS circuit design and layout optimization for the state-of-the-art CMOS image sensor technologies.