Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization

Abstract

In this paper, we proposed parasitic capacitance prediction methodology using Bayesian optimization to accelerate the iterative design process. The layout process while circuit design is inevitable since the effect of parasitic RC after layout increases as technology scaled down. However, the layout process consumes many time and human resources. To overcome this problem, we present Bayesian optimization based parasitic capacitance estimation methodology with parasitic capacitance modelling. Our proposed methodology can predict the parasitic capacitance of various inverter and NAND2 with less than 3.1% of error.