Physical Unclonable Function Using Programmable Delay Lines

Abstract

In this paper, we propose a novel Ring-Oscillator Physical Unclonable Functions (RO-PUF) architecture using Programmable Delay Lines (PDL) in Field Programmable Gate Arrays (FPGA). Our proposed PUF uses PDL to change the propagation path inside the Look Up Table (LUT), thereby changing the output of RO. Depending on the output of the changed RO, different response outputs occur for the same RO-PUF architecture and challenge input. We have examined how the challenge-response pairs of the proposed PUF structure change according to the PDL. Additionally, we have analyzed the performance changes of the proposed PUF, finding that HDinter showed a maximum difference of 7. 1248%, and HDintra showed a maximum difference of 3.9731%. We confirm that the performance of the proposed PUF structure can vary depending on the PDL, and our research results will provide an optimal PUF structure solution to enhance the performance of PUF.