Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET

Abstract

In this work, the effects of misalignment between gate and channel edges on performances of an ultra-thin vertical-pillar MOSFET are investigated by a series of device simulations. The operation characteristics of the device as a function of degree of misalignment that might frequently exist between the gate and channel edges, in the actual device fabrication, have been quantitatively analyzed. In case of gate-drain overlap, there is little change in current characteristics but significant decrease in Ion and increase in Ioff were observed, when an excessive underlap was established, accompanying non-ideal effects including subthreshold swing (S) degradation and drain-induced barrier lowering (DIBL). Based on the results, the process margin can be figured.