GATe: Streamlining Memory Access and Communication to Accelerate Graph Attention Network With Near-Memory Processing

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-04-10 DOI:10.1109/LCA.2024.3386734
Shiyan Yi;Yudi Qiu;Lingfei Lu;Guohao Xu;Yong Gong;Xiaoyang Zeng;Yibo Fan
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Abstract

Graph Attention Network (GAT) has gained widespread adoption thanks to its exceptional performance. The critical components of a GAT model involve aggregation and attention, which cause numerous main-memory access. Recently, much research has proposed near-memory processing (NMP) architectures to accelerate aggregation. However, graph attention requires additional operations distinct from aggregation, making previous NMP architectures less suitable for supporting GAT. In this paper, we propose GATe, a practical and efficient GAT acc e lerator with NMP architecture. To the best of our knowledge, this is the first time that accelerates both attention and aggregation computation on DIMM. In the attention and aggregation phases, we unify feature vector access to reduce repetitive memory accesses and refine the computation flow to reduce communication. Furthermore, we introduce a novel sharding method that enhances the data reusability. Experiments show that our work achieves substantial speedup of up to 6.77× and 2.46×, respectively, compared to state-of-the-art NMP works GNNear and GraNDe.
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GATe:简化内存访问和通信,利用近记忆处理加速图形注意网络
图形注意力网络(GAT)因其卓越的性能而得到广泛应用。图形注意力网络模型的关键组件包括聚合和注意力,它们会导致大量主内存访问。最近,许多研究提出了近内存处理(NMP)架构来加速聚合。然而,图注意需要与聚合不同的额外操作,这使得以前的 NMP 架构不太适合支持 GAT。在本文中,我们提出了 GATe,一种采用 NMP 架构的实用高效的 GAT 加速器。据我们所知,这是首次在 DIMM 上同时加速注意力和聚合计算。在注意和聚合阶段,我们统一了特征向量访问以减少重复内存访问,并改进了计算流程以减少通信。此外,我们还引入了一种新颖的分片方法,以提高数据的可重用性。实验表明,与最先进的 NMP 作品 GNNear 和 GraNDe 相比,我们的作品分别实现了高达 6.77 倍和 2.46 倍的大幅提速。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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