An Area Efficient Architecture of a Novel Chaotic System for High Randomness Security in e-Health

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-04-10 DOI:10.1109/LCA.2024.3387352
Kyriaki Tsantikidou;Nicolas Sklavos
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Abstract

An e-Health application must be carefully designed, as a malicious attack has ethical and legal consequences. While common cryptography protocols enhance security, they also add high computation overhead. In this letter, an area efficient architecture of a novel chaotic system for high randomness security is proposed. It consists of the chaotic logistic map and a novel component that efficiently combines it with a block cipher's key generation function. The proposed architecture operates as both a key scheduling/management scheme and a stream cipher. All operations are implemented in an FPGA with appropriate resource utilization techniques. The proposed architecture achieves smaller area consumption, minimum 41.5%, compared to published cryptography architectures and a 5.7% increase in throughput-to-area efficiency compared to published chaotic designs. Finally, it passes all NIST randomness tests, presents avalanche effect and produces the highest number of random bits with a single seed compared to other published security systems.
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用于电子医疗高随机性安全的新型混沌系统的面积效率架构
电子医疗应用必须经过精心设计,因为恶意攻击会带来道德和法律后果。虽然常见的加密协议能提高安全性,但也会增加高计算开销。在这封信中,我们提出了一种用于高随机安全性的新型混沌系统的高效面积架构。它由混沌逻辑图和一个将其与区块密码密钥生成功能有效结合的新型组件组成。所提出的架构既是密钥调度/管理方案,又是流密码。所有操作都通过适当的资源利用技术在 FPGA 中实现。与已发布的加密体系结构相比,拟议的体系结构实现了更小的面积消耗,最小为 41.5%;与已发布的混沌设计相比,吞吐量-面积效率提高了 5.7%。最后,与其他已发布的安全系统相比,它通过了所有 NIST 随机性测试,呈现出雪崩效应,并能以单个种子产生最高数量的随机比特。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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