Performance Enhancing of Nano-scale Technologies in Nuclear Applications Using C-MOS and FS-GDI Hybrid Approach

Abstract

Nano-scale technologies have gained significant attention in various industries, including the nuclear field, due to their unique properties and potential benefits such as miniaturization and improved performance, radiation-hardened electronics, sensors, and detectors. This paper studies the performance of the different Nano-scale technologies in electronic elements fabrication using the different Full Adder (FA) circuits with respect to different realizing methods. Four main parameters; delay time, consumed power, simplicity of hardware (number of transistors),and Power Delay Product (PDP) have been used for evaluating the different FA circuits efficiency in 45nm and 65 nm Nano-technologies and utilizing the Complementary Pass-Transistor Logic (CPL), Complementary Metal-Oxide-Semiconductor (C-MOS), Full-Swing Gate Diffusion Input (FS-GDI) hybrid approaches. The experiments are carried out using a simulator package (Cadence Virtuoso) for 65nm nanotechnology. The results revealed the performance of the FA circuits at the lower Nano-scale performed better than the higher nanoscale. C-MOS approaches provide better improvement in the 45 nm technology compared to the 65 nm technology and the other realizing approaches.