Dielectric pocket engineered, gate induced drain leakages (GIDL) and analog performance analysis of dual metal nanowire ferroelectric MOSFET (DPE-DM-NW-Fe FET) as an inverter

Shalu Garg, Jasdeep Kaur, Anubha Goel, Subhasis Haldar, R. S. Gupta
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Abstract

This research article presents a simulation study on a dielectric pocket engineered dual metal nanowire ferroelectric (DPE-DM-NW-Fe FET) MOSFET. The aim is to mitigate the Gate-Induced Drain Leakage (GIDL) effect in the off-state condition and improve the subthreshold swing. GIDL is a type of SCE which is detrimental for the device as continuous gate leakage current. Severely hamper the performance of the device particularly in analog applications. To prevent this a novel structure is proposed in which two dielectric pockets are introduced adjacent to the source and drain to reduce the SCEs. GIDL occurs even when the gate voltage is nearly zero, but it becomes significant when the gate region is at a lower bias and the drain region is at a higher bias. The introduced dielectric pockets act as diffusion stoppers, forming insulating barriers to prevent off-state current. Simulation studies were conducted to analyze off-state GIDL currents for different channel lengths (30 nm, 40 nm, and 50 nm). Various parameters such as electric field, electron concentration, electron velocity, and surface potential have been simulated and compared with a Single Metal Gate (SMG) cylindrical MOSFET. Critical performance parameters including drain current, transconductance (gm), output conductance (gd), input capacitance (CGG), cutoff frequency (fT), gain transconductance frequency product (GTFP), gain frequency product (GFP), maximum transfer power gain (MTPG), unilateral power gain (UPG), and early voltage (Vea) have been calculated. Additionally, the noise performances of the DPE-DM-NW-Fe FET have been examined, and its implementation as a CMOS inverter have been explored for determining noise margins. The lower noise margin makes the device suitable for high-frequency applications. The simulations have been conducted using the ATLAS-3D simulator.

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作为逆变器的双金属纳米线铁电 MOSFET(DPE-DM-NW-Fe FET)的介质袋工程、栅极诱导漏极漏电流(GIDL)和模拟性能分析
本文介绍了对介质袋工程双金属纳米线铁电(DPE-DM-NW-Fe FET)MOSFET 的仿真研究。其目的是减轻关态条件下的栅极诱导漏极漏电(GIDL)效应,并改善阈下摆幅。GIDL 是一种 SCE,由于持续的栅极漏电流而对器件造成损害。严重影响器件的性能,尤其是在模拟应用中。为了防止这种情况,我们提出了一种新型结构,在源极和漏极附近引入两个介质袋,以减少 SCE。即使栅极电压接近于零,也会出现 GIDL,但当栅极区处于较低偏压而漏极区处于较高偏压时,GIDL 就会变得非常明显。引入的电介质袋起到了扩散阻断器的作用,形成了绝缘壁垒,阻止了关态电流的产生。模拟研究分析了不同沟道长度(30 nm、40 nm 和 50 nm)的关态 GIDL 电流。模拟了电场、电子浓度、电子速度和表面电势等各种参数,并与单金属栅极(SMG)圆柱形 MOSFET 进行了比较。关键性能参数包括漏极电流、跨导 (gm)、输出电导 (gd)、输入电容 (CGG)、截止频率 (fT)、增益跨导频率乘积 (GTFP)、增益频率乘积 (GFP)、最大传输功率增益 (MTPG)、单边功率增益 (UPG) 和早期电压 (Vea)。此外,还研究了 DPE-DM-NW-Fe FET 的噪声性能,并探索了其作为 CMOS 逆变器的实现方法,以确定噪声裕量。较低的噪声裕量使该器件适用于高频应用。模拟是使用 ATLAS-3D 模拟器进行的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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