Design of a very low power 12 bits, 40 MS/s ADC based on a time-interleaved SAR architecture

Abstract

The paper describes a new figure of merit reachable in terms of very low power dissipation for a 12 bit, 40 MS/s Analog to Digital Converter in a 65 nm CMOS process with 1 V power supply. A differential time interleaved successive approximations register architecture is used. Each individual ADC channel is optimized with regard to power consumption hence interleaving 28 ADC channels in an analog memory like method, the total power consumption is only 280 μW including all the reference voltage drivers, the clock management and the digital sections. The total layout area of this converter is 0.87 mm2.