Erika S. Alcorta;Mahesh Madhav;Richard Afoakwa;Scott Tetrick;Neeraja J. Yadwadkar;Andreas Gerstlauer
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引用次数: 0
Abstract
Modern computer designs support composite prefetching, where multiple prefetcher components are used to target different memory access patterns. However, multiple prefetchers competing for resources can sometimes hurt performance, especially in many-core systems where cache and other resources are limited. Recent work has proposed mitigating this issue by selectively enabling and disabling prefetcher components at runtime. Formulating the problem with machine learning (ML) methods is promising, but efficient and effective solutions in terms of cost and performance are not well understood. This work studies fundamental characteristics of the composite prefetcher selection problem through the lens of ML to inform future prefetcher selection designs. We show that prefetcher decisions do not have significant temporal dependencies, that a phase-based rather than sample-based definition of ground truth yields patterns that are easier to learn, and that prefetcher selection can be formulated as a workload-agnostic problem requiring little to no training at runtime.
现代计算机设计支持复合预取,即使用多个预取器组件来针对不同的内存访问模式。然而,多个预取器竞争资源有时会影响性能,尤其是在缓存和其他资源有限的多核系统中。最近的研究提出了通过在运行时有选择地启用和禁用预取器组件来缓解这一问题。用机器学习(ML)方法来解决这个问题很有前景,但在成本和性能方面,高效和有效的解决方案还没有得到很好的理解。这项工作通过 ML 的视角研究了复合预取器选择问题的基本特征,为未来的预取器选择设计提供参考。我们的研究表明,预取器决策并不具有显著的时间依赖性,基于阶段而非基于样本的地面实况定义会产生更易于学习的模式,而且预取器选择可以表述为一个与工作负载无关的问题,几乎不需要运行时的训练。
期刊介绍:
IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.