Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-06-25 DOI:10.1109/LCA.2024.3418874

Mohammadamin Ajdari;Behrang Montazerzohour;Kimia Abdi;Hossein Asadi

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Abstract

In this paper, we first analyze a real storage system consisting of 72 SSDs utilizing either Hardware RAID (HW-RAID) or Software RAID (SW-RAID), and show that SW-RAID is up to 7× faster. We then reveal that with an increasing number of SSDs, the limited I/O parallelism in SAS controllers and multi-enclosure handshaking overheads cause a significant performance drop, minimizing the total I/O Per Second (IOPS) of a 144-SSD system to less than a single SSD. Second , we disclose the most important architectural parameters that affect a large-scale storage system. Third , we propose a framework that models a large-scale storage system and estimates the system IOPS and system resource usage for various architectures. We verify our framework against a real system and show its high accuracy. Lastly , we analyze a use case of a 240-SSD system and reveal how our framework guides architects in storage system scaling.

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有关 Petascale 全闪存存储系统性能可扩展性的经验架构分析

在本文中，我们首先分析了一个由 72 个固态硬盘组成的真实存储系统，该系统采用硬件 RAID（HW-RAID）或软件 RAID（SW-RAID），结果表明 SW-RAID 的速度最高可达 7 倍。然后，我们揭示了随着固态硬盘数量的增加，SAS 控制器中有限的 I/O 并行性和多机箱握手开销会导致性能大幅下降，从而将 144-SSD 系统的总每秒 I/O (IOPS) 降低到单个固态硬盘的水平。其次，我们揭示了影响大规模存储系统的最重要的架构参数。第三，我们提出了一个框架，该框架可对大规模存储系统进行建模，并估算各种架构下的系统 IOPS 和系统资源使用量。我们用实际系统验证了我们的框架，并展示了其高准确性。最后，我们分析了 240-SSD 系统的使用案例，揭示了我们的框架如何指导架构师进行存储系统扩展。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.