Highly Versatile FPGA-Implemented Cyber Coherent Ising Machine

Toru Aonishi, Tatsuya Nagasawa, Toshiyuki Koizumi, Mastiyage Don Sudeera Hasaranga Gunathilaka, Kazushi Mimura, Masato Okada, Satoshi Kako, Yoshihisa Yamamoto
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Abstract

In recent years, quantum Ising machines have drawn a lot of attention, but due to physical implementation constraints, it has been difficult to achieve dense coupling, such as full coupling with sufficient spins to handle practical large-scale applications. Consequently, classically computable equations have been derived from quantum master equations for these quantum Ising machines. Parallel implementations of these algorithms using FPGAs have been used to rapidly find solutions to these problems on a scale that is difficult to achieve in physical systems. We have developed an FPGA implemented cyber coherent Ising machine (cyber CIM) that is much more versatile than previous implementations using FPGAs. Our architecture is versatile since it can be applied to the open-loop CIM, which was proposed when CIM research began, to the closed-loop CIM, which has been used recently, as well as to Jacobi successive over-relaxation method. By modifying the sequence control code for the calculation control module, other algorithms such as Simulated Bifurcation (SB) can also be implemented. Earlier research on large-scale FPGA implementations of SB and CIM used binary or ternary discrete values for connections, whereas the cyber CIM used FP32 values. Also, the cyber CIM utilized Zeeman terms that were represented as FP32, which were not present in other large-scale FPGA systems. Our implementation with continuous interaction realizes N=4096 on a single FPGA, comparable to the single-FPGA implementation of SB with binary interactions, with N=4096. The cyber CIM enables applications such as CDMA multi-user detector and L0 compressed sensing which were not possible with earlier FPGA systems, while enabling superior calculation speeds, more than ten times faster than a GPU implementation. The calculation speed can be further improved by increasing parallelism, such as through clustering.
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高通用性 FPGA 实现的网络相干等效机
近年来,量子伊辛机引起了广泛关注,但由于物理实现方面的限制,量子伊辛机很难实现紧密耦合,如具有足够自旋的完全耦合,以处理实际的大规模应用。因此,人们从量子主方程中推导出了这些量子伊辛机的经典可计算方程。使用 FPGA 并行执行这些算法,可以快速找到解决这些问题的方法,而物理系统很难实现这种规模。我们开发了一种 FPGA 实现的网络相干伊兴机(cyber CIM),它比以前使用 FPGA 实现的网络相干伊兴机更具通用性。我们的架构具有多功能性,因为它既可以应用于 CIM 研究开始时提出的开环 CIM,也可以应用于最近使用的闭环 CIM,还可以应用于雅各布连续超松弛法。通过修改计算控制模块的序列控制代码,还可以实现模拟分岔(SB)等其他算法。早期关于 SB 和 CIM 的大规模 FPGA 实现的研究使用二进制或三元离散值进行连接,而网络 CIM 使用的是 FP32 值。此外,网络 CIM 还利用了以 FP32 表示的泽曼项,这在其他大规模 FPGA 系统中是不存在的。我们在单个 FPGA 上实现了 N=4096 的连续交互,与单个 FPGA 实现二进制交互的 SB(N=4096)相当。网络 CIM 使 CDMA 多用户检测器和 L0 压缩传感等应用成为可能,而这些应用在早期的 FPGA 系统上是不可能实现的。通过增加并行性(如通过聚类),计算速度还能进一步提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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