Accelerating Programmable Bootstrapping Targeting Contemporary GPU Microarchitecture

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-06-24 DOI:10.1109/LCA.2024.3418448
Hyesung Ji;Sangpyo Kim;Jaewan Choi;Jung Ho Ahn
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Abstract

Fully homomorphic encryption (FHE) enables computation on encrypted data without privacy leakage, among which GSW-based schemes are notable for supporting the evaluation of arbitrary univariate functions using programmable bootstrapping (PBS). Despite their wide applicability, their computational complexity in a single PBS impedes widespread adoption. However, at the application level, there are enough number of independent PBSs to achieve high data-level parallelism, making them suitable for running on GPUs known for their high parallel computing capability. On contemporary GPUs, peak integer performance has steadily increased, and the sizes of L2 cache and shared memory have also grown rapidly since the Volta architecture. Prior attempts to accelerate PBS on GPUs have fallen short due to their outdated implementations that cannot leverage recent GPU advances. In this paper, we introduce a GPU implementation that supports the latest PBS algorithm and incorporates GPU-trend-aware optimizations. Our implementation achieves a 10.8× performance improvement over the state-of-the-art (SOTA) GPU implementations on RTX 4090 and even outperforms the SOTA ASIC implementation.
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加速以当代 GPU 微体系结构为目标的可编程引导
全同态加密(FHE)可在不泄露隐私的情况下对加密数据进行计算,其中基于 GSW 的方案因支持使用可编程引导(PBS)对任意单变量函数进行评估而备受瞩目。尽管它们具有广泛的适用性,但单个 PBS 的计算复杂性阻碍了它们的广泛应用。然而,在应用层面上,有足够数量的独立 PBS 可以实现数据级的高度并行性,使它们适合在以高并行计算能力著称的 GPU 上运行。在当代 GPU 上,整数峰值性能稳步提升,二级缓存和共享内存的大小自 Volta 架构以来也迅速增长。之前在 GPU 上加速 PBS 的尝试都因其过时的实现而失败,无法充分利用 GPU 的最新进展。在本文中,我们介绍了一种支持最新 PBS 算法的 GPU 实现,并结合了 GPU 趋势感知优化。与 RTX 4090 上最先进的(SOTA)GPU 实现相比,我们的实现提高了 10.8 倍的性能,甚至优于 SOTA ASIC 实现。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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