Pragmatics of Formally Verified Yet Efficient Static Analysis, in particular for Formally Verified Compilers

David MonniauxVERIMAG - IMAG
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Abstract

Formally verified compilers and formally verified static analyzers are a solution to the problem that certain industries face when they have to demonstrate to authorities that the object code they run truly corresponds to its source code and that it satisfies certain properties. From a scientific and technological point of view, they are a challenge: not only a number of nontrivial invariants and algorithms must be proved to be correct, but also the implementation must be reasonably effective so that the tools operate within reasonable time. Many optimizations in compilers rely on static analysis, and thus a formally verified compiler entails formally verified static analyses.In this article, we explain some difficulties, possible solutions, design choices and trade-offs pertaining to verified static analysis, in particular when the solution of the analysis is expressed as some form of tree, map or set.
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形式验证但高效静态分析的实用性,尤其是针对形式验证编译器的静态分析
正式验证的编译器和正式验证的静态分析器可以解决某些行业所面临的问题,即它们必须向权威机构证明所运行的目标代码真正对应于其源代码,并满足某些属性。从科学和技术的角度来看,它们是一项挑战:不仅要证明许多非琐碎的不变式和算法是正确的,而且实施必须合理有效,以便工具能在合理的时间内运行。编译器中的许多优化都依赖于静态分析,因此一个经过形式验证的编译器需要经过形式验证的静态分析。在本文中,我们将解释与经过验证的静态分析有关的一些困难、可能的解决方案、设计选择和权衡,特别是当分析的解决方案以某种形式的树、映射或集合表示时。
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