Performance evaluation of superconductor integrated circuit simulators

Abstract

The development of superconductor integrated circuits (SCIC) places increasing demands on electronic design automation (EDA) tools. Circuit simulation is a crucial step in the design process of superconducting quantum interference devices (SQUID) and single flux quantum (SFQ) circuits. Over the years, there have been many SC circuit simulators, like JSPICE, JSIM, WRspice, JoSIM, PSCAN2, JSICsim, PrimeSim HSPICE, Spectre, and more. The previous studies have compared the differences in results among some simulators for the same circuit cases. However, designers of SC circuits still face challenges when choosing simulators and setting simulation parameters. The performance of these simulators lacks comprehensive and quantitative evaluations to date. To evaluate the performance of the simulators, we focused on three aspects: the differences among the IV results, accuracy, and speed. For characterizing the accuracy of the simulators, we proposed a method that uses the relative error between the numerical and analytical solutions at the $L$-$C$ resonance point on the IV curve of a dc SQUID. In this article, we have selected five representative simulators JoSIM, JSIM, WRspice, PSCAN2, and JSICsim for our study. By using multiple cases of the bare and coupled dc SQUID, multiple IV curves, and the analytical solution as a reference, we comprehensively compared the performance of these simulators. Additionally, we quantitatively examined the impact of two key simulation parameters, namely, the maximum allowed simulation timestep (max timestep) and relative tolerance (RelTol), on the performance of these simulators. Our results show that the normalized voltage differences in the IV curves of different simulators are relatively small (within 0.06) in regions far from the $L$-$C$ resonance point, while they increase significantly near the $L$-$C$ resonance point (maximum is 0.4). PSCAN2 exhibits a significant relative error of approximately 16% when the max timestep is 0.6ps and RelTol is $1\times 10^{-1}$, which is close to its default RelTol value. Our work provides some insights and references for the designers of SC circuits on how to choose simulators and set simulation parameters.