A 56 Gb/s DAC-DSP-based transmitter with adaptive retiming clock optimization using inverse-PR-based PD achieving 8-UI converge time in 28-nm CMOS

Abstract

This work presents an adaptive clock optimization scheme for TX to alleviate the timing constraints for the retimer. Using the PR and inverse-PR-based phase detector, the optimal clock phase is selected for retiming with only 8 UI convergence time. By adopting the proposed technique, we realize a 1–56 Gb/s DAC-DSP-based TX in 28-nm CMOS. Measurement results show that the rising edge of retiming clock is located in the center of data when the phase adjustment completed. The total TX consumes 164 mWat 56-Gb/s PAM4 signaling with 97.8% RLM in 0.25 mm² area. Therefore, the proposed retiming clock optimization scheme is a promising scheme for high-speed TX.