Area Efficient Skyrmion Logic Based Approximate Adder Architecture Design Methodology

Abstract

In this study, the first of its kind skyrmion logic based area efficient approximate nanomagnetic (APN) adder architecture design methodology is introduced along with its implementation using theoretical modelling and micromagnetic simulations. We propose here for the first time, skyrmion based APN adder architecture design using only one majority gate reconfigured runtime (RR) using single layout. This low complex device structure is modelled using three inputs with the bilayer ferromagnet/heavy metal utilizing the exploitation of output reversal mechanism using magnetic tunnel junctions (MTJs) for read and write of skyrmions. The implementation is performed using this same device where current is passed through a metallic gate for control mechanism to achieve various logic functionalities. We also introduce here the boolean optimzation followed by mapping logic for the demonstration of skyrmion RRAPN adder alongside the majority logic gate. This proposed RRAPN adder architecture design possess low complexity in terms of utilization of resources aiding towards the reduction of number of majority logic gates ($ \sim$$60 \%$ device footprint reduction) and evaluated against standard error metrics. RRAPN adder architecture design proposed has its advantages with miniaturisation aided by enhanced lithographic process nodes, creating a new potential for nanomagnetic logic devices.