{"title":"Investigating the 20T Hybrid Full Adder Design for Low Power and High-Performance Computing","authors":"Satvik Goel, Saurabh Kumar, Ritam Tripathi, Shivansh Bajpai, Rahul Soni, R.K. Chauhan","doi":"10.1080/03772063.2024.2387292","DOIUrl":null,"url":null,"abstract":"The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thoroug...","PeriodicalId":50375,"journal":{"name":"IETE Journal of Research","volume":"59 1","pages":""},"PeriodicalIF":1.3000,"publicationDate":"2024-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IETE Journal of Research","FirstCategoryId":"94","ListUrlMain":"https://doi.org/10.1080/03772063.2024.2387292","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract
The 1-bit full adder is a crucial building block in digital circuits, widely used in various applications such as arithmetic circuits, digital filters, and computer memory. In this study, a thoroug...
期刊介绍：
IETE Journal of Research is a Bimonthly journal published by the Institution of Electronics and Telecommunication Engineers (IETE), India. It publishes scientific and technical papers describing original research work or novel product/process development. Occasionally special issues are brought out on new and emerging research areas.
IETE Journal of Research is useful to researchers, engineers, scientists, teachers, managers and students who are interested in keeping a track of original research and development work being carried out in the broad area of electronics, telecommunications, computer science and engineering and information technology.
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