Chip-Backside Vulnerability to Intentional Electromagnetic Interference in Integrated Circuits

Abstract

The backside of integrated circuits (ICs) in flip-chip assembly is susceptible to intentional electromagnetic interference due to its open surface. In this article, we propose a model in which conducted current noise from a localized area of the Si substrate on the chip-backside causes errors in complementary metal-oxide-semiconductor (CMOS) digital circuits. This model explains for the first time the mechanism of bit-flip errors in bistable circuits caused by high-voltage pulse (HVP) injection on the backside of the IC. The injected current from the backside of the IC not only flows into the power distribution network, but also charges the gate capacitance of the next stage via p–n junction diodes of body/drain or body/source in N-channel mosfet s (NMOS) with twin-well structures, resulting in bit-flip errors. In this study, circuit simulations were performed using a three-dimensional RC network model of the IC chip and an HVP injector. These simulations have shown that the P-well voltage is biased depending on the arrangement of the tap cells, reproducing bit-flip errors in the bistable circuit of a D flip-flop. The simulation results were validated on a fabricated prototype IC chip, which confirmed the trend of data dependency for errors related to the physical layout.