An Efficient Characterization Method to Predict the Susceptibility of Integrated Circuits to Multitone Disturbance

IF 2.5 3区 计算机科学 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Electromagnetic Compatibility Pub Date : 2024-09-04 DOI:10.1109/TEMC.2024.3448495
Alexandre Boyer;Fabrice Caignet;Matthieu Laidet
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Abstract

With the growing concerns about the safety of electronic equipment in complex electromagnetic environments, the characterization and prediction of integrated circuits (ICs) susceptibility to multitone disturbance become more and more urgent. This article proposes an efficient method to characterize the response of an IC to multitone disturbance, based on a conventional continuous wave (CW) susceptibility test followed by a large-band injection test. The proposed test aims to verify the application of the disturbance superposition principle of an IC terminal. If it applies, the risk of failure due to any combination of harmonic disturbances can be determined from the usual CW susceptibility test results. The only difference is that the radiofrequency (RF) synthesizer is replaced by an arbitrary waveform generator in order to produce a comb signal composed of several equidistant harmonics with equal amplitude. The article presents the approach, the proposed indicators to test the disturbance superposition principle assessment and the validation results of the method applied to six different ICs, presenting different functions and technologies (op-amp, bandgap reference, dc–dc converter, digital gates, microcontroller I/O). In spite of the nonlinear reaction of the tested IC to electromagnetic disturbance, the results show that the disturbance superposition principle applies as long as one failure mechanism is activated. The validation of this principle on an IC simplifies substantially the electromagnetic compatibility (EMC) risk assessment when the IC is exposed to a complex combination of harmonic disturbances, as demonstrated by the experimental results presented in this article.
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预测集成电路受多音干扰影响程度的高效特征描述方法
随着人们对复杂电磁环境下电子设备安全性的日益关注,集成电路对多音干扰敏感性的表征和预测变得越来越迫切。本文提出了一种有效的方法来表征集成电路对多音扰动的响应,该方法基于传统的连续波(CW)敏感性试验和大波段注入试验。本实验旨在验证干扰叠加原理在集成电路终端上的应用。如果适用,任何谐波干扰组合引起的失效风险可以从通常的连续波敏感性试验结果中确定。唯一的区别是射频(RF)合成器被任意波形发生器取代,以产生由几个等距谐波组成的梳状信号。本文介绍了该方法,提出了测试干扰叠加原理评估的指标,并将该方法应用于六种不同的ic,具有不同的功能和技术(运算放大器,带隙参考,dc-dc转换器,数字门,微控制器I/O)。尽管被测集成电路对电磁干扰具有非线性反应,但结果表明,只要激活一种失效机制,干扰叠加原理就适用。当集成电路暴露于复杂的谐波干扰组合时,该原理在集成电路上的验证大大简化了电磁兼容性(EMC)风险评估,如本文中提出的实验结果所示。
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来源期刊
CiteScore
4.80
自引率
19.00%
发文量
235
审稿时长
2.3 months
期刊介绍: IEEE Transactions on Electromagnetic Compatibility publishes original and significant contributions related to all disciplines of electromagnetic compatibility (EMC) and relevant methods to predict, assess and prevent electromagnetic interference (EMI) and increase device/product immunity. The scope of the publication includes, but is not limited to Electromagnetic Environments; Interference Control; EMC and EMI Modeling; High Power Electromagnetics; EMC Standards, Methods of EMC Measurements; Computational Electromagnetics and Signal and Power Integrity, as applied or directly related to Electromagnetic Compatibility problems; Transmission Lines; Electrostatic Discharge and Lightning Effects; EMC in Wireless and Optical Technologies; EMC in Printed Circuit Board and System Design.
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