Exploiting Intrinsic Redundancies in Dynamic Graph Neural Networks for Processing Efficiency

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-12-07 DOI:10.1109/LCA.2023.3340504
Deniz Gurevin;Caiwen Ding;Omer Khan
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Abstract

Modern dynamical systems are rapidly incorporating artificial intelligence to improve the efficiency and quality of complex predictive analytics. To efficiently operate on increasingly large datasets and intrinsically dynamic non-euclidean data structures, the computing community has turned to Graph Neural Networks (GNNs). We make a key observation that existing GNN processing frameworks do not efficiently handle the intrinsic dynamics in modern GNNs. The dynamic processing of GNN operates on the complete static graph at each time step, leading to repetitive redundant computations that introduce tremendous under-utilization of system resources. We propose a novel dynamic graph neural network (DGNN) processing framework that captures the dynamically evolving dataflow of the GNN semantics, i.e., graph embeddings and sparse connections between graph nodes. The framework identifies intrinsic redundancies in node-connections and captures representative node-sparse graph information that is readily ingested for processing by the system. Our evaluation on an NVIDIA GPU shows up to 3.5× speedup over the baseline setup that processes all nodes at each time step.
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利用动态图神经网络的内在冗余提高处理效率
现代动态系统正在迅速融入人工智能,以提高复杂预测分析的效率和质量。为了高效地处理日益庞大的数据集和内在动态的非欧几里得数据结构,计算界已转向图神经网络(GNN)。我们发现一个关键问题,即现有的图神经网络处理框架无法有效处理现代图神经网络的内在动态性。GNN 的动态处理在每个时间步都对完整的静态图进行操作,导致重复的冗余计算,造成系统资源的极大利用不足。我们提出了一种新颖的动态图神经网络(DGNN)处理框架,它能捕捉动态图神经网络语义的动态演化数据流,即图嵌入和图节点之间的稀疏连接。该框架可识别节点连接中的内在冗余,并捕捉具有代表性的节点稀疏图信息,以便系统随时进行处理。我们在英伟达™(NVIDIA®)图形处理器上进行的评估显示,与在每个时间步处理所有节点的基线设置相比,速度提高了 3.5 倍。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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