Low power and energy efficient design of ternary D-latch based on CNTFET-RRAM technology

Abstract

This paper presents a ternary D-latch design using resistive random-access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The property of multi-threshold in CNTFETs and multi-level cell in RRAM is utilized in designing ternary logic circuits. The advantages of ternary logic provide best substitute to replace conventional binary logic system such as less interconnect complexity, enhanced information density, compact chip area and fast computational ability. As a result, the ternary system offers digital designs that are easy to implement while maintaining both high energy efficiency and rapid signal processing. This paper presents a ternary D-latch circuit utilizing CNTFET-RRAM based ternary logic gates including standard ternary inverter (STI) and ternary NAND (TNAND). The proposed design provides 0.863 nW power consumption and 12 ps delay.