Design of a novel CMOS instrumentation amplifier using 90 nm technology

Abstract

In this article, a novel Complementary Metal Oxide Semiconductor (CMOS) instrumentation amplifier is designed using UMC 90 nm technology with an operating power supply of ± 0.9 V. A differential and operational amplifier with improved gain and low power dissipation were also designed. Because of the ease with which gain may be varied, instrumentation amplifiers have traditionally been preferred. Instead of passive-resistive loads, NMOS is used as active loads (in linear region behaves like a resistor), reducing the die area and lowering power consumption. As a result, active loads produce greater resistance values than passive loads, leading to higher power gains. Previous studies of two-stage Op-Amps have shown that the overall gain is lowered when there is a resistive load at the output. Another issue with a two-stage Op-Amps is the trade-off between speed and gain. An instrumentation amplifier with 97.69 dB differential gain and 135.72 dB common mode rejection ratio (CMRR) has been attained utilising Cadence virtuoso environment UMC 90 nm CMOS process, and the layout area of proposed design with padding is 79.005 μm × 85.17 μm.