A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-09-18 DOI:10.1109/JSSC.2024.3456889
Yu-Chen Lo;Yi-Chung Wu;Chia-Hsiang Yang
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引用次数: 0

Abstract

This article presents the first dedicated processor designed to support the complete spectral unmixing workflow for hyperspectral image (HSI) processing, including rank reduction, endmember extraction, and abundance estimation. The design employs architecture explorations, including folding and data interleaving, to reduce hardware complexity. To enhance the throughput, the processor incorporates deeply pipelined reconfigurable processing elements (PEs) for compute-intensive tasks involved in spectral unmixing. The proposed sparsity-adaptive clocking technique leverages data sparsity and minimizes dynamic power consumption. Fabricated in a 40-nm CMOS technology, the proposed processor occupies a core area of 2.56 mm2. The chip consumes 44.3 mW of power at a clock frequency of 175 MHz from a 0.68-V supply. The processor can concurrently generate eight endmembers and their associated abundances for a ${256}{\times }{ 256}{\times }64$ HSI, resulting in a throughput of 62.4 fps. Comparative analysis with a high-end CPU demonstrates a significant processing speed improvement of $544{\times }$ , accompanied by energy efficiency that is 1735 $537{\times }$ higher and area efficiency that is 31 $647{\times }$ higher. The proposed processor is $17.5{\times }$ faster, with 236 $735{\times }$ higher energy efficiency and $4158{\times }$ higher area efficiency in comparison to a high-end graphics processing unit (GPU). The proposed processor provides a promising solution to support real-time hyperspectral remote sensing, particularly for battery-powered micro air vehicles (MAVs).
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用于飞行器遥感中光谱解混的 44.3 毫瓦 62.4 帧/秒高光谱图像处理器
本文介绍了第一个专用处理器,旨在支持用于高光谱图像(HSI)处理的完整光谱分解工作流程,包括秩降阶,端元提取和丰度估计。该设计采用架构探索,包括折叠和数据交错,以降低硬件复杂性。为了提高吞吐量,处理器结合了深度流水线可重构处理元素(pe),用于涉及光谱分解的计算密集型任务。本文提出的稀疏性自适应时钟技术利用了数据稀疏性和最小化动态功耗。该处理器采用40纳米CMOS技术制造,核心面积为2.56 mm2。该芯片在时钟频率为175 MHz时,从0.68 v电源消耗44.3 mW的功率。处理器可以并发地以${256}{\times}{256}{\times}64$ HSI生成8个端元及其相关丰度,从而产生62.4 fps的吞吐量。与高端CPU的对比分析表明,处理速度显著提高544美元,能效提高1735美元537美元,面积效率提高31美元647美元。与高端图形处理单元(GPU)相比,拟议的处理器速度快17.5美元,能效高236美元,面积效率高4158美元。该处理器为支持实时高光谱遥感提供了一个有前途的解决方案,特别是对于电池供电的微型飞行器(MAVs)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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