A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars

IF 4.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-09-25 DOI:10.1109/JSSC.2024.3460178
Francesco Tesolin;Simone M. Dartizio;Giacomo Castoro;Francesco Buccoleri;Michele Rossoni;Carlo Samori;Andrea L. Lacaita;Salvatore Levantino
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Abstract

This article describes a 10-GHz chirp generator for frequency-modulated continuous-wave (FMCW) radars, that is based on a digital PLL (DPLL) with a two-point injection of the modulation signal. A new digital predistortion (DPD) algorithm is introduced that is specifically tailored to mitigate the impact of the nonlinear non-smooth tuning curve of a digitally controlled oscillator (DCO) optimized for a low phase noise. The algorithm estimates in the background a non-uniform piecewise parabolic (PWP) interpolation of the digital inverse of the DCO tuning curve, using an adaptive set of non-uniformly distributed breakpoints. The breakpoints are automatically placed at the corner points of the tuning characteristic. The chirp generator, implemented in a 28-nm CMOS process, dissipates 21 mW and generates sawtooth and triangular chirp frequency modulations with slope up to 680 MHz/ $\mu $ s and bandwidth up to 680 MHz, while keeping the rms frequency error below 150 kHz and the phase noise at 1-MHz offset at −116.5 dBc/Hz.
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一种基于 10 GHz 数字 PLL 的啁啾发生器,具有用于 FMCW 雷达的抛物线非均匀数字预失真功能
本文介绍了一种用于频率调制连续波(FMCW)雷达的 10 GHz 啁啾发生器,该发生器基于数字 PLL(DPLL),调制信号采用两点注入方式。该算法专门用于减轻数字控制振荡器(DCO)非线性非平滑调谐曲线对低相位噪声的影响。该算法使用一组非均匀分布的自适应断点,在背景中对数字控制振荡器调谐曲线的非均匀片状抛物线(PWP)数字逆插值进行估计。这些断点自动放置在调谐特性的角点上。啁啾发生器采用 28 纳米 CMOS 工艺实现,功耗为 21 mW,可产生锯齿形和三角形啁啾频率调制,斜率高达 680 MHz/ $\mu$s,带宽高达 680 MHz,同时保持均方根频率误差低于 150 kHz,1 MHz 偏移时的相位噪声为 -116.5 dBc/Hz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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Modular DR-and CMR-Boosted Artifact-Resilient EEG Headset With Distributed Pulse-Based Feature Extraction and Neuro-Inspired Boosted-SVM Classifier Table of Contents Table of Contents IEEE Journal of Solid-State Circuits Publication Information Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC)
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