Real-Time Digital RF Emulation—Part II: A Near Memory Custom Accelerator

Abstract

A near memory hardware accelerator, based on a novel direct path computational model (DPCM), for real-time emulation of radio frequency (RF) systems is demonstrated. Our evaluation of hardware performance uses both application-specific integrated circuits (ASICs) and field programmable gate array (FPGA) methodologies: 1) the ASIC test-chip implementation, using Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm CMOS, leverages distributed autonomous control to extract concurrence in compute as well as low latency. It achieves a 518 MHz per channel bandwidth in a prototype four-node system. The maximum emulation range supported in this paradigm is 9.5 km with $0.24~\mu $ s of per-sample emulation latency and 2) the FPGA-based implementation, evaluated on a Xilinx ZCU104 board, demonstrates a nine-node test case (two transmitters, one receiver, and six passive reflectors) with an emulation range of 1.13–27.3 km at 215-MHz bandwidth.