25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies

Abstract

We present an NRZ/PAM-3 dual-mode transmitter featuring a 9-bit/6-UI-based embedded partial data bus inversion (pDBI). In this design, if the number of “1”s exceeds three in the initial 6-bit/4-UI segment of the 9-bit/6-UI PAM-3 data, the data are inverted to reduce the signaling current. A pDBI masking bit is inserted in the final 3-bit/2-UI segment to utilize a vacant 1-bit position left in every 8-bit sequence due to the memory’s burst length (BL) specification. This configuration eliminates the need for a DBI pin, thereby improving pin efficiency. Compared to previous data bus inversion (DBI) schemes used in NRZ and PAM-3 signaling, our proposed pDBI scheme significantly improves DBI, pin, and I/O bandwidth/pin efficiencies. Additionally, our design supports a single-loop ZQ calibration for both NRZ and PAM-3 modes, employing one-point calibration in NRZ and two-point calibration in PAM-3, ensuring optimal ratio of level mismatch (RLM) in PAM-3. A prototype chip, fabricated using a 65-nm CMOS process, achieved data rates of 14 Gb/s in NRZ mode and 25.2 Gb/s in PAM-3 mode under the -4.4-dB channel loss at 8.4 GHz. We also verified a peak DBI efficiency of 19.3% and measured an RLM of 98.5% in PAM-3 mode with the two-point ZQ calibration.