A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing

Abstract

Combinatorial optimization problems (COPs) are essential in various real-world decision-making scenarios, yet most COPs are classified as non-deterministic polynomial-time (NP) hard or complete, posing significant computational challenges. Traditional von Neumann computing architectures often incur high energy costs and prolonged computational latencies when tackling COPs. Recently, researchers have used continuous-time (CT) Ising machines as low-cost COP solvers due to their attractive solving speed. However, prior CT works suffer from inadequate coefficient precision, the lack of annealing mechanisms, and susceptibility to variations. In light of this, this work presents an in-eDRAM mixed-signal CT Ising machine featuring eDRAM-based compute-in-memory (CIM) architecture. It introduces a current-based multi-level interaction topology for updating spins and presents a CT annealing mechanism to access the ground energy landscape. To enhance its process, voltage, and temperature (PVT) robustness, the two-step current-programming technique is used to eliminate mismatches caused by PVT variations. The prototype chip with a $32\times 33$ spin array is fabricated using a 65-nm CMOS process. Each spin occupies an area of 848 $\mu $ m2, including 20 3T1C current-programmed eDRAMs and eight 1T1C eDRAMs. Measurement results demonstrate that the proposed CT Ising machine has excellent PVT robustness, the lowest normalized spin area ( $13.6~\mu $ m2), and the highest coefficient level of 15. It can solve multi-level max-cut problems on a nanosecond timescale and consumes only 0.33–1.05 nJ at a 1.0–1.2-V core supply voltage.