{"title":"A High-Efficiency 12/1-V Dual-Path Series-Capacitor Converter With Low V⋅A Metric and Full Duty Range","authors":"Xu Yang;Linhu Zhao;Zhichao Tan;Menglian Zhao;Yong Ding;Wuhua Li;Wanyuan Qu","doi":"10.1109/JSSC.2024.3464122","DOIUrl":null,"url":null,"abstract":"This article presents a dual-path series-capacitor (DPSC) converter with a voltage range of <inline-formula> <tex-math>$9~{\\sim }~16$ </tex-math></inline-formula>-V input to 1-V output. By forming a capacitive-current path with flying capacitors, the proposed DPSC converter alleviates both voltage and current stresses on both the inductor and switches, enhancing overall efficiency and achieving the lowest <inline-formula> <tex-math>$V\\cdot A$ </tex-math></inline-formula> metric for the switches. The proposed DPSC converter enables inherent full duty cycle operation and reduced inductor current. The prototype converter demonstrates a measured peak efficiency of 94.5% with a maximum load capacity of 5 A. Besides, the proposed converter can be easily compatible with existing light-load schemes, which shows 89.2% at 0.1-A load for this design. The DPSC converter maintains high efficiency throughout the voltage conversion ratios (VCRs) and load ranges, outperforming prior state-of-the-art solutions.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1731-1742"},"PeriodicalIF":5.6000,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10701036/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents a dual-path series-capacitor (DPSC) converter with a voltage range of $9~{\sim }~16$ -V input to 1-V output. By forming a capacitive-current path with flying capacitors, the proposed DPSC converter alleviates both voltage and current stresses on both the inductor and switches, enhancing overall efficiency and achieving the lowest $V\cdot A$ metric for the switches. The proposed DPSC converter enables inherent full duty cycle operation and reduced inductor current. The prototype converter demonstrates a measured peak efficiency of 94.5% with a maximum load capacity of 5 A. Besides, the proposed converter can be easily compatible with existing light-load schemes, which shows 89.2% at 0.1-A load for this design. The DPSC converter maintains high efficiency throughout the voltage conversion ratios (VCRs) and load ranges, outperforming prior state-of-the-art solutions.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.