A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition

Abstract

As the most compute-intensive signal processing task in the global positioning system (GPS) receiver, signal acquisition accounts for most of the power budget, which is a key bottleneck in extending the battery life of edge devices. To improve the energy efficiency of GPS signal acquisition, we present charge-domain computing for GPS signal acquisition (CCSA), a matched filter with CCSA. It employs a $64 {\times } 64$ mixed-signal processing element (PE) array, a 2.8-b flash analog-to-digital converter (ADC), and a digital controller. Each PE handles the element-wise multiplication with a mixed-signal multiplier (MSMUL), which can perform the multiplication and digital-to-charge conversion simultaneously with a two-phase operation scheme. We develop the two-phase digital-to-charge mapping method for the MSMUL, where the digital multiplication result is converted into the charge difference stored in a capacitor between the charge reset phase and the charge evaluation phase. The charge-domain outputs of all MSMULs are dumped and redistributed on a global output wire for the accumulation operation. Compared to prior charge-domain works, the proposed design reduces the number of capacitors or additional voltage levels by half, thereby leading to better energy efficiency and lower circuit complexity. The 28-nm test chip achieves 114–394-TOPS/W energy efficiency across 0.34–0.9-V supply voltage, which is $8.2{\times }$ higher than state-of-the-art at the same throughput.