{"title":"ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM","authors":"Wenao Xie;Haoyang Sang;Beomseok Kwon;Dongseok Im;Sangjin Kim;Sangyeob Kim;Kangho Lee;Hoi-Jun Yoo","doi":"10.1109/JSSC.2024.3470033","DOIUrl":null,"url":null,"abstract":"This study introduces an event-driven smart vision system-on-chip (SoC) using a reconfigurable and high-linearity magnetoresistive random access memory (MRAM) processing-in-memory (PIM) architecture. It features a double differential MRAM PIM column with dual complementary 4T4R cells for enhanced MAC operation accuracy and a dynamic 2T2R–4T4R macro for adjustable precision and throughput. Incorporating an aggregation pipeline (AGP) and the intra- and inter-cluster mapping schemes, the reconfigurable PIM achieves improved utilization and energy efficiency. The system also offers a multi-level and crossover event detection mechanism via binary similarity computing for adaptable object recognition in varying conditions. Fabricated with 28-nm FD-SOI technology, the SoC encompasses a die area of <inline-formula> <tex-math>$9.72~{\\text {mm}^{2}}$ </tex-math></inline-formula> with 128 kb of MRAM cell capacity, integrating a 64-bit RISC-V core, and an 8-bit grayscale CMOS sensor with <inline-formula> <tex-math>$128 \\times 128$ </tex-math></inline-formula> pixel resolution. The SoC demonstrates up to 709.3-TOPS/W macro-level energy efficiency at 200 MHz for 1-bit input/weight and 3-bit output. It also attains an average end-to-end system efficiency of 7.57 TOPS/W when performing 8-bit ResNet-20 inference with accuracies of 91.90% and 67.61% on the CIFAR-10/100 datasets. The SoC significantly reduces core power consumption to 7.3 mW in moving object detection, achieving a 30.9% power reduction over conventional non-event-driven designs.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 6","pages":"2226-2238"},"PeriodicalIF":5.6000,"publicationDate":"2024-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10714470/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This study introduces an event-driven smart vision system-on-chip (SoC) using a reconfigurable and high-linearity magnetoresistive random access memory (MRAM) processing-in-memory (PIM) architecture. It features a double differential MRAM PIM column with dual complementary 4T4R cells for enhanced MAC operation accuracy and a dynamic 2T2R–4T4R macro for adjustable precision and throughput. Incorporating an aggregation pipeline (AGP) and the intra- and inter-cluster mapping schemes, the reconfigurable PIM achieves improved utilization and energy efficiency. The system also offers a multi-level and crossover event detection mechanism via binary similarity computing for adaptable object recognition in varying conditions. Fabricated with 28-nm FD-SOI technology, the SoC encompasses a die area of $9.72~{\text {mm}^{2}}$ with 128 kb of MRAM cell capacity, integrating a 64-bit RISC-V core, and an 8-bit grayscale CMOS sensor with $128 \times 128$ pixel resolution. The SoC demonstrates up to 709.3-TOPS/W macro-level energy efficiency at 200 MHz for 1-bit input/weight and 3-bit output. It also attains an average end-to-end system efficiency of 7.57 TOPS/W when performing 8-bit ResNet-20 inference with accuracies of 91.90% and 67.61% on the CIFAR-10/100 datasets. The SoC significantly reduces core power consumption to 7.3 mW in moving object detection, achieving a 30.9% power reduction over conventional non-event-driven designs.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.