A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS

Abstract

This article presents a long-reach (LR) capable, 224 Gb/s pulse amplitude modulation 4-level (PAM-4) wireline transceiver solution achieving 1e−6 bit error rate (BER) with a 40 dB insertion loss channel, while operating with an analog energy efficiency of 3 pJ/bit. The transmitter (TX) comprises a 7-bit current mode digital to analog converter (DAC) operating with 1/8 rate, timing calibrated clocks, and achieves 55 fsrms random and 170 fs deterministic jitter. The receiver (RX) includes 20 dB peaking gain from an inverter-based analog front-end (AFE) and a 7-bit, time-interleaved analog to digital converter (ADC). Transmitter and receiver rely on a shared 14 GHz clock that is generated by an all-digital, bang-bang phase locked loop (PLL). To address high loss applications, the embedded receiver digital signal processing (DSP) is equipped with a maximum likelihood decision detector in addition to a decision feedback equalizer (DFE). The serializer/deserializers (SerDes) macro with four transceiver lanes is fabricated in a 3-nm FinFET CMOS technology and occupies 0.5 mm2 per transceiver lane.