A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs

Abstract

Computing-in-memory (CIM) architectures have demonstrated remarkable potential in addressing the memory wall. However, previous CIMs were often designed for multiply-accumulate (MAC) operations, which presents a myriad of challenges when deploying graph convolutional networks (GCNs) on CIM macros. This work presents a compact 6T SRAM-based aggregation and combination CIM macro (ACCIM) using: 1) a cell array with compact 6T bitcells, local jump and computing cells (LJCCs), and sparse-tracking analog-to-digital converters (STADCs) to improve energy efficiency in both input sparsity and weight bit sparsity; 2) an LJCC and STADC to improve the signal margin; 3) a CIM macro architecture with an aggregation input unit (AGINU) to support both GCN aggregation and GCN combination/convolutional neural network (CNN) MAC; 4) a graph pruning algorithm that divides the graph data into memory-friendly subgraphs; and 5) an error modeling-based pre-training method to improve the inference accuracy. A fabricated 28-nm 16-kb charge-domain SRAM-CIM macro achieved an energy efficiency of 86.87 TOPS/W and an area efficiency of 2344 GOPS/mm2 for GCNs with 4-bit degree input, 8-bit features, and 15-bit output.