{"title":"Flip-Chip Aperture Coupled D-Band Active Radiator Tiles in 22-nm CMOS FDSOI","authors":"Alex Ayling;Ali Hajimiri","doi":"10.1109/JSSC.2024.3485062","DOIUrl":null,"url":null,"abstract":"A <inline-formula> <tex-math>${2} {\\times } {2}$ </tex-math></inline-formula> D-band active radiator tile is designed in 22-nm CMOS fully depleted silicon on insulator (FDSOI). The tile uses commercial materials, fabrication, and assembly techniques while relaxing printed circuit board (PCB) requirements by eliminating D-band routing. This is accomplished by fully integrating the D-band signal generation, amplification, phase shifting, and antenna coupling structures onto the chip. The phase shifting is accomplished without requiring I/Q generation using the on-chip frequency multipliers. The on-chip power amplifiers (PAs) directly excite off-chip patch antennas via aperture coupling from the chip to the PCB, avoiding the need for costly transitions off-chip. The tile is aligned and assembled with the antenna using flip-chip bonding, which also provides all the low-frequency interconnects for the chip. A <inline-formula> <tex-math>${2} {\\times } {4}$ </tex-math></inline-formula> array using two of the tiles, demonstrating the scalability of the system, achieves a narrow inter-chip element spacing of <inline-formula> <tex-math>$0.6{\\lambda }$ </tex-math></inline-formula> at 140 GHz, a peak effective isotropic radiated power (EIRP) of +23.5 dBm, and a scan range of ±40° while dissipating 77 mW per element.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 6","pages":"1932-1946"},"PeriodicalIF":5.6000,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10741957","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10741957/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A ${2} {\times } {2}$ D-band active radiator tile is designed in 22-nm CMOS fully depleted silicon on insulator (FDSOI). The tile uses commercial materials, fabrication, and assembly techniques while relaxing printed circuit board (PCB) requirements by eliminating D-band routing. This is accomplished by fully integrating the D-band signal generation, amplification, phase shifting, and antenna coupling structures onto the chip. The phase shifting is accomplished without requiring I/Q generation using the on-chip frequency multipliers. The on-chip power amplifiers (PAs) directly excite off-chip patch antennas via aperture coupling from the chip to the PCB, avoiding the need for costly transitions off-chip. The tile is aligned and assembled with the antenna using flip-chip bonding, which also provides all the low-frequency interconnects for the chip. A ${2} {\times } {4}$ array using two of the tiles, demonstrating the scalability of the system, achieves a narrow inter-chip element spacing of $0.6{\lambda }$ at 140 GHz, a peak effective isotropic radiated power (EIRP) of +23.5 dBm, and a scan range of ±40° while dissipating 77 mW per element.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.