Flip-Chip Aperture Coupled D-Band Active Radiator Tiles in 22-nm CMOS FDSOI

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-11-04 DOI:10.1109/JSSC.2024.3485062
Alex Ayling;Ali Hajimiri
{"title":"Flip-Chip Aperture Coupled D-Band Active Radiator Tiles in 22-nm CMOS FDSOI","authors":"Alex Ayling;Ali Hajimiri","doi":"10.1109/JSSC.2024.3485062","DOIUrl":null,"url":null,"abstract":"A <inline-formula> <tex-math>${2} {\\times } {2}$ </tex-math></inline-formula> D-band active radiator tile is designed in 22-nm CMOS fully depleted silicon on insulator (FDSOI). The tile uses commercial materials, fabrication, and assembly techniques while relaxing printed circuit board (PCB) requirements by eliminating D-band routing. This is accomplished by fully integrating the D-band signal generation, amplification, phase shifting, and antenna coupling structures onto the chip. The phase shifting is accomplished without requiring I/Q generation using the on-chip frequency multipliers. The on-chip power amplifiers (PAs) directly excite off-chip patch antennas via aperture coupling from the chip to the PCB, avoiding the need for costly transitions off-chip. The tile is aligned and assembled with the antenna using flip-chip bonding, which also provides all the low-frequency interconnects for the chip. A <inline-formula> <tex-math>${2} {\\times } {4}$ </tex-math></inline-formula> array using two of the tiles, demonstrating the scalability of the system, achieves a narrow inter-chip element spacing of <inline-formula> <tex-math>$0.6{\\lambda }$ </tex-math></inline-formula> at 140 GHz, a peak effective isotropic radiated power (EIRP) of +23.5 dBm, and a scan range of ±40° while dissipating 77 mW per element.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 6","pages":"1932-1946"},"PeriodicalIF":5.6000,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10741957","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10741957/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

Abstract

A ${2} {\times } {2}$ D-band active radiator tile is designed in 22-nm CMOS fully depleted silicon on insulator (FDSOI). The tile uses commercial materials, fabrication, and assembly techniques while relaxing printed circuit board (PCB) requirements by eliminating D-band routing. This is accomplished by fully integrating the D-band signal generation, amplification, phase shifting, and antenna coupling structures onto the chip. The phase shifting is accomplished without requiring I/Q generation using the on-chip frequency multipliers. The on-chip power amplifiers (PAs) directly excite off-chip patch antennas via aperture coupling from the chip to the PCB, avoiding the need for costly transitions off-chip. The tile is aligned and assembled with the antenna using flip-chip bonding, which also provides all the low-frequency interconnects for the chip. A ${2} {\times } {4}$ array using two of the tiles, demonstrating the scalability of the system, achieves a narrow inter-chip element spacing of $0.6{\lambda }$ at 140 GHz, a peak effective isotropic radiated power (EIRP) of +23.5 dBm, and a scan range of ±40° while dissipating 77 mW per element.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
采用 22 纳米 CMOS FDSOI 的倒装芯片孔径耦合 D 波段有源辐射器瓦片
采用22nm CMOS全贫硅绝缘体(FDSOI)设计了一种d波段有源辐射片。瓷砖使用商业材料,制造和组装技术,同时通过消除d波段路由放松印刷电路板(PCB)要求。这是通过将d波段信号产生、放大、相移和天线耦合结构完全集成到芯片上来实现的。相移无需使用片上乘频器产生I/Q即可完成。片上功率放大器(PAs)通过从芯片到PCB的孔径耦合直接激发片外贴片天线,避免了昂贵的片外转换的需要。瓦片使用倒装芯片键合与天线对齐和组装,倒装芯片也为芯片提供所有的低频互连。使用两个磁片的${2}{\times}{4}$阵列显示了系统的可扩展性,在140 GHz时实现了$0.6{\lambda}$的窄片间元件间距,峰值有效各向同性辐射功率(EIRP)为+23.5 dBm,扫描范围为±40°,每个元件的功耗为77 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
期刊最新文献
A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1